In a non-volatile (NV) memory, an individual memory cell may include a single charge storing transistor. As an example of NV memory, in a NAND type flash memory, a plurality of memory cells are arranged in an array including a plurality of rows and columns of interconnected memory cells. The memory cells are interconnected by a plurality of word lines and bit lines, each cell in a row being connected by a common word line, for example, and each cell in a column being connected by at least one common bit line. The common word line is typically connected to a gate of each transistor of a memory cell in the row, while the common bit line is typically connected to a source or drain of each transistor of a memory cell in the column.
In some NV memory, such as, for example, the NAND type flash memory, the plurality of memory cells may be managed or controlled according to a hierarchical structure. For example, an array of memory cells are grouped into one or more blocks, and each block is divided into one or more physical pages, each corresponding to a word line. A physical page is the basic programming unit in a NV memory, such that the group of memory cells constituting a physical page can be programmed together during a programming process, such as a write operation. The number of memory cells constituting a physical page may be determined based on the number of memory cells controlled by a common word line. In some hierarchies, the memory cells of a common word line (i.e., physical page) may be divided into more than one physical unit. Additionally, a physical unit may include memory cells controlled by more than one word line.
Memory cells of a flash memory are typically programmed and erased by applying a particular voltage to the word line and one or more bit lines of the targeted memory cells to be programmed or erased. Over time, a plurality of program/erase operations may wear on the transistors making up the memory cells causing them to change properties, resulting in a bit error in a memory cell and potentially in neighboring memory cells. This wear or degradation of the transistors can change the performance and reliability of the plurality of memory cells, potentially making them unusable. A useful life of a NV memory is commonly represented by the number of program/erase cycles (P/E) that a memory cell can withstand before the memory cell becomes unusable. In some systems, once a memory cell has experienced a predetermined number of P/E cycles or demonstrated degraded properties, the memory cells are considered unusable and retired from future use.
Typically, in a NV memory, such as flash memory, a logical-to-physical mapping of memory cells is designed at a block level. Thus, when some memory cells of a block become unusable, the hierarchical block including the degraded or unusable memory cells is retired even if not all of the memory cells of the block are degraded or unusable. And as block sizes are becoming larger and larger in NV memory devices, this conventional block retirement scheme imposes a significant penalty on the storage capabilities of the memory device. Because the degree of wear or degradation of the memory cells constituting individual physical pages may vary considerably within a single block (e.g., due to uneven P/E operations on the physical pages), the conventional block retirement schemes may unnecessarily retire usable memory cells, resulting in wasted storage capacity.